Description

The Leidos Innovations Center has an immediate opening for a mid-level FPGA Engineer to work in San Diego, CA. This is an exciting opportunity to leverage your experience to develop and produce advanced nuclear detection, radiography equipment, chemical and biological sensing instruments and satellite sensor systems. Emphasis is on research and development with activities ranging from support of early scientific research to transitioning products to production.

Primary Responsibilities

• Motivated self-starter able to work under minimal supervision, and an entrepreneurial approach to roles and responsibilities.
• Good oral/written communication, interpersonal skills, and ability to coordinate work with others.
• Develop and test FPGA designs for Chemical, Biological, Radiation, Nuclear, and Space sensor systems for federal government customers.
• Execute FPGA test plans, determine root cause of test failures, and iterate with senior staff to determine design changes to improve FPGA performance.
• Support electrical engineering activities including FPGA designs and system integration and testing with CAD and lab activities.
• Collaborate in scientific research, engineering product development, and test activities. Contribute to design reviews and present designs for review.
• Work independently and use judgement to perform engineering task with uncertain and evolving requirements.
• Use judgment to perform technical troubleshooting and diagnosis of failed equipment and support root cause analysis.
• Perform data analysis and write technical reports.
• 0-20% travel to customer sites as required.

Preferred Responsibilities:

• Collaborate with a multi-disciplined design team to design and integrate DSP applications for latest System on a Chip (SoC) implementations such as Xilinx Zynq Ultrascale+ and Xilinx RFSoC.
• Analyze, design, and implement HDL test benches in hardware description languages, HDL (VHDL, Verilog), for code validation and validation against models.
• Bring up FPGA PCBs and test hardware in lab using oscilloscopes, logic analyzers, network analyzers,

Basic Qualifications

• B.S. degree or higher in Engineering, Physics, Mathematics, or related field from an accredited college/university with 6-8+ years of relevant experience
• Must be a US Citizen and have the ability to obtain a Secret security clearance.
• Must have proven course-work for FPGA or ASIC designs, Digital design. Perform FPGA designs using VHDL/Verilog/SystemVerilog

Preferred Qualifications

• Current active Secret security clearance or higher.
• Master's degree, with 4-6+ years of relevant experience.
• DSP algorithm development background including Matab/Python coding
• Experience leading small teams on projects or tasks

While subject to change based on business needs, Leidos reasonably anticipates that this job requisition will remain open for at least 3 days with an anticipated close date of no earlier than 3 days after the original posting date as listed above.

The Leidos pay range for this job level is a general guideline onlyand not a guarantee of compensation or salary. Additional factors considered in extending an offer include (but are not limited to) responsibilities of the job, education, experience, knowledge, skills, and abilities, as well as internal equity, alignment with market data, applicable bargaining agreement (if any), or other law.